1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to flash memory devices.
2. Discussion of Related Art
In general, a flash memory device includes a page buffer for programming or reading a large capacity of data for a short period of time. The page buffer includes high-voltage elements and low voltage elements. Accordingly, in the manufacture process of the flash memory device, a part of the page buffer is formed in a high-voltage element region of a semiconductor substrate and the remaining portions are formed in a low voltage element region of the semiconductor substrate.
FIG. 1 is a schematic layout diagram of a part of a flash memory device in the related art. FIG. 1 shows a memory cell region CL, a high-voltage element region HV, and a low-voltage element region LV. The memory cell region CL is a region in which memory cells are formed. The high-voltage element region HV and the low-voltage element region LV are regions in which circuits of the flash memory device are formed. For the simplicity of the drawing, only regions corresponding to the page buffers are shown in FIG. 1.
In the high-voltage element region HV, reference numerals “HPB1” to “HPB4” denote regions in which bit line selection circuits of the page buffers are formed (hereinafter, referred to as “bit line selection circuit regions”). Furthermore, in the low-voltage element region LV, reference numerals “LPB1” to “LPB4” denote regions in which register circuits of the page buffers are formed (hereinafter, referred to as “register circuit regions”). As a result, page buffer regions PBF1 to PBF4 having the bit line selection circuit regions HPB1 to HPB4, respectively, and the register circuit regions LPB1 to LPB4, respectively, are disposed on one side of the memory cell region CL. For example, the page buffer region PBF1 may include the bit line selection circuit region HPB1 and the register circuit region LPB1.
Sensing lines SOL1 to SOL4 are further disposed in order to form electrical paths between the bit line selection circuit regions HPB1 to HPB4 and the register circuit regions LPB1 to LPB4, which are disposed in different regions. The sensing lines SOL1 to SOL4 are disposed on the bit line selection circuit regions HPB1 to HPB4 and the register circuit regions LPBL to LPB4, respectively, and also cross the bit line selection circuit regions HPB1 to HPB4 and the register circuit regions LPB1 to LPB4, respectively. Since the page buffer regions PBF1 to PBF4 are arranged adjacent to each other, the sensing lines SOL1 to SOL4 are also arranged adjacent to each other. If the sensing lines SOL1 to SOL4 are disposed adjacent to each other as described above, interference may occur between signals respectively transferred to the sensing lines SOL1 to SOL4 due to parasitic capacitance C existing between the sensing lines SOL1 to SOL4 in the read operation of the flash memory device. This will be described in more detail below.
An example in which read data of “1” (i.e., VCC) are transferred through the sensing line SOL2 and read data of “0” (i.e., VSS) are transferred through the sensing lines SOL1, SOL3 during the read operation may be considered. In this case, a page buffer connected to the sensing line SOL2 may erroneously sense that the read data of the sensing line SOL2 is “0”. This is because the sensing line SOL2 must be kept to the voltage (VCC) level although the sensing lines SOL1, SOL3 become the voltage (VSS) level, but a voltage of the sensing line SOL2 is reduced as a result of the coupling capacitance of the parasitic capacitance C.
If the voltage of the sensing line SOL2 is reduced as described above, the page buffer connected to the sensing line SOL2 may erroneously sense that a logic value of read data transferred to the sensing line SOL2 is “0” not “1”. As a result, the read data transferred to the sensing lines SOL1 to SOL4, respectively, may be erroneously sensed by the page buffers due to an interference phenomenon between the sensing lines SOL1 to SOL4. Such a phenomenon becomes more profound as semiconductor memory devices are further miniaturized and more highly integrated, causing the distance between the sensing lines to be gradually reduced.
Furthermore, the interference phenomenon between the sensing lines causes failure in the read operation or the normal read operation for program verification of the flash memory device.